Synopsys Validates PCIe 6.0 PHY in 3D Stack, Leveraging 2D Test Chip

Synopsys Pushes PCIe 6.0 into 3D Stacking

Synopsys has announced a significant milestone in high-speed interconnect technology: the silicon validation of a Peripheral Component Interconnect Express (PCIe) 6.0 Physical Layer (PHY) operating within a face-to-face 3D stacked package. This achievement, running at the demanding 64 GT/s data rate, represents a crucial step towards denser, more powerful computing architectures. The company reports that it accomplished this by repurposing an existing 2D test chip, demonstrating a pragmatic approach to accelerating advanced packaging validation.

The core of this development is Synopsys's PCIe 6.0 PHY, designed to meet the stringent requirements of next-generation data rates. PCIe 6.0, based on the PAM4 signaling standard, doubles the bandwidth of PCIe 5.0 while maintaining backward compatibility. This involves sophisticated signal integrity management and error correction mechanisms to ensure reliable data transfer at speeds where signal degradation is a primary concern.

What sets this validation apart is its execution within a face-to-face 3D stacked package. In this configuration, two or more semiconductor dies are stacked directly on top of each other, with electrical connections made between them without the need for an interposer. This approach offers substantial advantages in terms of reduced latency, increased bandwidth density, and a smaller overall footprint compared to traditional 2D packaging. For high-performance applications like AI accelerators, high-performance computing (HPC), and advanced networking, minimizing latency and maximizing bandwidth are paramount. A 3D stacked architecture directly addresses these needs by shortening the physical distance signals must travel between components.

The decision to leverage an existing 2D test chip for this validation is particularly noteworthy. Instead of designing a completely new chip optimized solely for 3D stacking from the ground up, Synopsys has demonstrated the adaptability of its existing IP. This suggests a strategy focused on rapid iteration and validation of advanced packaging technologies by intelligently re-using and re-purposing proven silicon. This method can significantly reduce development time and cost, allowing companies to explore the benefits of 3D stacking sooner.

Technical Underpinnings and Validation Process

The validation was performed on a 5nm process technology, indicating the leading-edge manufacturing capabilities required for such high-speed interfaces. The PCIe 6.0 PHY itself is a complex piece of IP, handling the physical transmission and reception of data. This includes components like the SerDes (Serializer/Deserializer) which converts parallel data to serial for transmission and vice-versa for reception, clock data recovery circuits, and equalization techniques to compensate for signal loss and distortion across the interconnects.

Operating at 64 GT/s, each lane of the PCIe 6.0 interface transmits data at a rate of 8 gigabytes per second (GB/s) in each direction, thanks to the PAM4 signaling which encodes two bits per symbol. This is a significant leap from the 32 GT/s of PCIe 5.0. Achieving this speed reliably within a stacked package introduces unique challenges. Signal integrity can be affected by the proximity of other active components in the stack, thermal management becomes more critical, and the interconnects between the stacked dies must be robust and low-loss.

Synopsys’s approach involved integrating their PCIe 6.0 PHY IP into a test chip that was then subjected to a face-to-face stacking process. The validation involved rigorous testing to confirm that the PHY could establish and maintain a stable link at 64 GT/s, not just between the PHY and external interfaces, but also across the inter-die connections within the 3D stack. This silicon-level confirmation is essential for building confidence in the technology for commercial deployment.

The fact that an existing 2D test chip was used implies that Synopsys likely adapted their design to interface correctly with the chosen stacking technology and potentially modified some aspects of the SerDes or equalization to account for the different channel characteristics of a 3D stack. This reuse strategy is a smart way to de-risk the adoption of new packaging paradigms. It allows engineers to focus on the challenges of the stack itself, rather than simultaneously debugging a novel PHY design and a novel packaging solution.