Project Oberon Runs on RISC-V, Reviving Classic OS on New Architecture

A Classic OS Reimagined for Modern Hardware

Project Oberon, a minimalist and influential operating system known for its integrated development environment and pioneering object-oriented design, has found a new lease on life. A dedicated developer, Rochus Keller, has successfully ported a version of the Oberon System to the RISC-V architecture. This move is significant not just for preserving a piece of computing history but for making it relevant to contemporary hardware, particularly the rapidly growing RISC-V ecosystem.

The original Oberon System, developed at ETH Zurich in the late 1980s and early 1990s, was designed for simplicity, elegance, and efficiency. It featured a tightly integrated graphical user interface, compiler, and operating system, all within a remarkably small footprint. Its philosophy emphasized a single, unified development environment and a focus on modularity and extensibility. This new port aims to carry that philosophy forward onto a modern, open-standard instruction set architecture.

The primary goal of this project, as detailed on its GitHub repository, is to provide a working Oberon System that runs natively on RISC-V processors. This is not a mere emulation; it's a direct port that leverages the RISC-V instruction set. The choice of RISC-V is strategic. As an open-source Instruction Set Architecture (ISA), RISC-V is gaining traction in various fields, from embedded systems and IoT devices to high-performance computing. Bringing a system like Oberon to this architecture opens up new possibilities for education, research, and the development of specialized embedded systems where Oberon's unique characteristics might offer advantages.

The technical challenge lies in adapting the Oberon System, which was originally designed for specific hardware architectures like the MIPS or ARM processors, to the RISC-V ISA. This involves recompiling the core system components, ensuring compatibility with RISC-V’s register set, memory model, and instruction encoding. The project specifically targets the RV32 variant of RISC-V, which is common in microcontrollers and embedded applications, making it a practical target for this type of operating system.

Technical Details and Implementation

Rochus Keller's implementation focuses on the Oberon V4 system, a later iteration that built upon the foundations of the original Oberon and Component Pascal. The porting effort involves a custom toolchain. This includes adapting the Oberon compiler itself to generate RISC-V code. The system's bootloader and kernel must also be re-engineered to interact correctly with RISC-V hardware specifics. This is a deep dive into the system's architecture, requiring a thorough understanding of both Oberon and RISC-V internals.

The project aims to achieve a self-hosting compiler, meaning the Oberon compiler running on the RISC-V port can itself compile Oberon code for the RISC-V architecture. This is a critical milestone for any operating system development, as it demonstrates the system's ability to evolve and be maintained on its target platform. Achieving self-hosting on a new architecture like RISC-V is a testament to the robustness of the Oberon design and the diligence of the porting effort.

One of the key aspects of this port is its potential application in educational settings. Oberon's integrated environment and clear object-oriented paradigm make it an excellent platform for teaching computer science concepts. By running on accessible and increasingly popular RISC-V hardware, it can provide students with a hands-on experience of systems programming and operating system design on modern, open hardware. This contrasts with many traditional educational systems that rely on older, proprietary architectures or complex virtualized environments.

The decision to target RISC-V is not arbitrary. The open nature of the ISA means it is free from licensing fees and vendor lock-in, fostering innovation. For a system like Oberon, which itself embodies principles of openness and simplicity, RISC-V is a natural fit. It allows the system to be deployed on a wide range of custom hardware designs and embedded devices without the constraints associated with proprietary architectures.

Implications and Future Directions

The successful port of Project Oberon to RISC-V opens up several avenues. For embedded systems developers, it offers a mature, well-understood operating system with a unique development model that could be suitable for specific applications requiring reliability and a small footprint. The integrated nature of Oberon can simplify development workflows for certain types of projects.

For researchers, this port provides a new platform for experimenting with operating system concepts, programming language design, and compiler technology on a modern, open architecture. The ability to study and modify a complete, self-contained system like Oberon on RISC-V could lead to new insights and innovations.

The surprising detail here is not the existence of a RISC-V port, as open-source systems frequently find their way to new architectures. Instead, it is the specific choice of Oberon, a system that, while historically significant, is not commonly seen in modern development discussions. Its revival on RISC-V suggests a deliberate effort to explore niche but powerful computing paradigms on hardware that is poised to become ubiquitous. This project demonstrates that the principles of Oberon's design — simplicity, integration, and elegance — still hold value and can be successfully applied to contemporary technological challenges.

What remains to be seen is the extent to which this port will be adopted. Will it remain a niche project for enthusiasts and educators, or will its utility in specific embedded contexts lead to broader adoption? The path forward will likely depend on community engagement, further development of supporting tools, and the ongoing growth of the RISC-V ecosystem itself. However, the accomplishment of bringing such a unique system to a modern architecture is a significant technical feat in itself.